A fine pitch BGA is what I classify 0.5mm pitch parts and lower. This article is strictly for this sized BGA. First off, you'll notice that a cost effective dog bone via can't fit between the pads under the BGA. Here is your first mandatory trade off toward a 'premium' technology. Your new via will be a called a 'plated - non-conductive-epoxy-filled-via' (or 'plated-via-in-pad for short). This is the cheapest of the Vias to place under a fine pitch BGA. It consists of a 6 mil drill, filled with epoxy, then plated over leaving a flat surface for the BGA ball to reflow on. Incidentally, I always specify a 5.9 drill on my drill chart so the PCB fab house will know which ones are which in case I use non filled vias of the same size elsewhere. My via pad stack is a 6 mil drill with annular ring of 14 mil, with a copper clearance of 25 mil.
Now, one cost effective approach to PCB designs in general is to use the least layer count as possible*. My first escape layer is the top layer. If you took all the BGA balls on the outside ring of the part, and escape on the top layer, you don't even need a via. This is valuable because a via will take valuable real-estate on all layers when it's used.
The second row in will need a via. This will need to escape on the bottom layer. Now, this is where a lot of people get separated from the pack. As an experienced PCB designer, I will recognize that when ever you use a via, all layers are affected by that via. A via takes up valuable space on all the inner layers. But, if you build your via stack up correctly, you will save space by not creating the annular ring on the inside layers. This is almost a mandatory requirement for a PCB design with a uBGA. In other words, your via will look like a dumbbell. Two rings on the ends, and a thin pipe connecting the two. The reason the second row must escape the bottom layer, is because a via requires a top and bottom, but not necessarily any inner rings. And if you fail to utilize this bottom layer for escaping, you won't get a chance to use it to escape from any other row of the BGA. The rings are there whether you use them or not, so it's best to use them.
Now, from the 3rd row in, you'll be escaping on inner layers. But, like the 2nd row's via, you'll need to create a via pad stack that removes the annular ring on the layers that you don't escape from. And since your using the inner layers, you're via will now look like a dumbbell with an extra ring in the middle. Mentor PADS, if set up properly, will create these via stack ups for you on the fly, while Orcad Layout does not, so if you're using the later, you'll need to create a special via for each row. The reason for leaving the rings off the layers that your not escaping from, is to leave room for other traces to squeeze through. You can't squeeze between a via with a rings, but you can if the rings are missing. And, when escaping through these vias with no rings, You'll need the trace to 'neck-down' to a 4 mil trace to squeeze between them. Any questions at this point, feel free to contact us. Our PCB design services department have all kind of techniques, including the expoxy filled via you'll read about here, that focus on low cost PCB implementations.
Now, if you've noticed, the 1st and 2nd rows have the chance for very fat traces. Hopefully, the chip designer will take this into consideration and placed any high current pins or pins that need decoupling caps on the first and second row.
*My biggest concern for designing a PCB in general, is cost. Some might say 'function' should come first, but to me, that's a given. And keep in mind, every premium technology or addition step that you add to the PCB fabrication process, you're adding cost. If you're going to use a laser drilled via on your PCB design, don't use a 6 mill via in addition. Also, if you decide to escape the 2nd row from the top layer, you'll need to neck down to a 3 mil trace. This might save 2 layers if you're lucky, but it's a huge cost adder, and in the end, keeping the 2 layers on your PCB design will save more money than that added premium.
There are so many technologies used on PCBs these days, it's easy for your marketing department to get stuck on the idea that lower layer count is the cheaper. That's not always true these days. In fact, that statement can be more damaging to the company as a whole, because you have the chip designers, marketing, and even the CEO thinking that way, and what ends up happening in the end, is a much higher cost of implementation for the customer, not to mention the possibility of decreased performance because a decoupling cap is routed with a 3 mil trace on your PCB design.
