A while back, I got a call from a company that asked for help with fixing their PCB design. They said that the DDR memory simply wasn't working and they have no idea what was wrong. Even though the board was based on the reference schematic and used the same parts it just didn't work.
The schematic and PCB design files were sent over and within the first 5 minutes the problem was solved. A technician made a few modifications based on some recommendations and low and behold, it started working in their lab.
The problem wasn't in the schematic, but in the PCB itself. The PCB designer of the original PCB had created a big break in the ground plane between the memory and the processor. And about 2 inches away from where the DDR memory data lines crossed over this abyss, was the connection tying the two ground planes back together again.
On PCB designs with high speed traces (including high speed memory such as with this case), a signal propagates down the PCB trace to the destination, and an equal and opposite amount of energy will travel the opposite direction, from the destination back to the source. This is called the current return path and is quite often ignored while designing a PCB. This return current will try to follow directly under the trace, on the plane that it's directly above (or below), and if a split in the plane is seen, it must make it's away around this break in the plane to return to the destination. In this case, it was adding 4 inches to it's flight time. There are other considerations regarding stitching together high speed AC currents together between planes, but that is beyond the scope of this article.
To help show the recommend solution to the developer, I created two 3D simulation models that represented the original problem PCB design with the break in the plane, and one without the break. The traces on this problem DDR buss were about 6 inches long, and because of a desire to keep PCB fabrication costs to a minimum, a standard layer thickness of 8 mil was chosen. The traces themselves were 6 mil wide, which yielded a trace impedance of around ~72-74Ohms (not exactly ideal impedance, but because of a tight real-estate issues on the PCB design, this was the best that could be done. However, with proper matching techniques, this impedance is not a problem). And finally, I used the IBIS models of the DDR memory part and processor to finish up my PCB simulation model.
Using the broken ground plane for my first simulation, I validated that this broken plane on the original PCB design was a huge problem. Simulating the DDR signal at the destination showed a very rounded and low voltage signal that was clearly not even producing a logic high. I found myself using 'virtual' zero ohm termination resistors, just as the original developers did on their real PCB, just to try and produce an acceptable signal. However, I knew I would never get the signal I needed, as this first simulation was simply a verification for the client that the problem is reproducible. (Photo below)
Onto the solid plane simulation setup. Everything was kept the same except the plane directly under the signals were now solid. And while using proper inline termination, I was able to produce a much better signal. The developer was able to keep the very low cost PCB design stack up that was desired, and an accurate inline termination resistor was derived from the simulation that gave very acceptable results for this particular DDR memory implementation. (Photo below).
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